1. Field of the Invention
The present invention relates to a D-FF circuit. In particular, the present invention relates to a D-FF circuit which is operated in accordance with a clock signal generated by a clock signal generating circuit.
2. Description of the Related Art
According to an earlier development, a D-flip-flop (hereinafter, referred to as xe2x80x9cD-FFxe2x80x9d) made from CMOS (Complementary MOS) comprises a flip-flop for a master part (hereinafter, referred to as xe2x80x9cmaster FFxe2x80x9d), a flip-flop for a slave part (hereinafter, referred to as xe2x80x9cslave FFxe2x80x9d) and a clock signal generating circuit. The clock signal generating circuit generates a clock signal to output the clock signal to the master FF and the slave FF. The master FF and the slave FF start or stop each operation at each timing in accordance with the outputted clock signal, respectively.
With reference to FIGS. 4 and 5, a D-FF circuit 100 according to an earlier development, will be explained.
FIGS. 4A and 4B are views showing a D-FF circuit made from CMOS according to an earlier development. FIG. 4A is a view showing a D-FF circuit 100. FIG. 4B is a view showing a clock signal generating circuit 200 of the D-FF circuit 100. FIG. 5 is a timing chart showing an operation of the D-FF circuit 100 according to an earlier development.
In FIG. 4A, the D-FF circuit 100 comprises a master FF having inverters 101 and 102, transfer gates G11 and G12 and a NAND gate 106, and a slave FF having transfer gates G13 and G14, a NAND gate 107 and inverters 103, 104 and 105. The master FF and the slave FF start or stop each operation in accordance with the clock signal outputted from the clock signal generating circuit 200, respectively.
The transfer gates G11, G12, G13 and G14 comprise P-channel transistors Tr35 to Tr38 and N-channel transistors Tr31 to Tr34, respectively. The clock signal outputted from the clock signal generating circuit 200 is inputted into each transistor Tr31 to Tr38. Each transfer gate G11, G12, G13 and G14 is in an xe2x80x9cONxe2x80x9d state or in an xe2x80x9cOFFxe2x80x9d state according to the clock signal inputted into each transistor Tr31 to Tr38. These transfer gates hold or transmit an input signal data.
As shown in FIG. 4B, the clock signal generating circuit 200 comprises two inverters 201 and 202. The inverter 201 inverts an input clock signal CLK to output a first clock signal {overscore (CLK1)}. The inverter 202 inverts the first clock signal {overscore (CLK1)} outputted from the inverter 201 to output a second clock signal CLK1.
The transfer gate G11 connects the output of the inverter 202 of the clock signal generating circuit 200 (the second clock signal CLK1) with a gate of the P-channel transistor Tr35. Further, the transfer gate G11 connects the output of the inverter 201 of the clock signal generating circuit 200 (the first clock signal {overscore (CLK1)}) with a gate of the N-channel transistor Tr31. Therefore, when the second clock signal {overscore (CLK1)} is in a xe2x80x9cHxe2x80x9d level and the first clock signal {overscore (CLK1)} is in a xe2x80x9cLxe2x80x9d level, the transfer gate G11 is in an xe2x80x9cOFFxe2x80x9d state and stops the operation of the master FF. The transfer gate G11 holds an input signal data.
The transfer gate G13 connects the output of the inverter 201 of the clock signal generating circuit 200 (the first clock signal {overscore (CLK1)}) with a gate of the P-channel transistor Tr37. Further, the transfer gate G13 connects the output of the inverter 202 of the clock signal generating circuit 200 (the second clock signal CLK1) with a gate of the N-channel transistor Tr33. Therefore, when the second clock signal CLK1 is in a xe2x80x9cHxe2x80x9d level and the first clock signal CLK1 is in a xe2x80x9cLxe2x80x9d level, the transfer gate G13 is in an xe2x80x9cONxe2x80x9d state and starts the operation of the slave FF.
That is, in the D-FF circuit 100 according to an earlier development, the phases of two signals (the first clock signal {overscore (CLK1)} and the second clock signal CLK1) are inverted. The clock signals are used as a clock signal for stopping the operation of the master FF and a clock signal for starting the operation of the slave FF, respectively.
In the timing chart shown in FIG. 5, when a xe2x80x9cHxe2x80x9d level input signal data is inputted at the time t40, the inverter 101 inverts the input signal data to output it. At the time t41, the voltage of the input signal data falls from a xe2x80x9cHxe2x80x9d level to a xe2x80x9cLxe2x80x9d level at a node N31. Because the transfer gate G11 is in an xe2x80x9cONxe2x80x9d state at the same time, the inverted input signal data outputted from the inverter 101 is transmitted. Next, the inverter 102 inverts the signal transmitted from the transfer gate G11 to output it. Then, at the time t43, the voltage of the signal rises from a xe2x80x9cLxe2x80x9d level to a xe2x80x9cHxe2x80x9d level at a node N33.
On the other hand, when a xe2x80x9cHxe2x80x9d level input clock signal CLK is inputted into the clock signal generating circuit 200 at the time t42, the inverter 201 inverts the input clock signal CLK to output a xe2x80x9cLxe2x80x9d level first clock signal {overscore (CLK1)}. That is, at the time t44, the voltage of the first clock signal {overscore (CLK1)} falls from a xe2x80x9cHxe2x80x9d level to a xe2x80x9cLxe2x80x9d level. The inverter 202 inverts the first clock signal {overscore (CLK1)} to output a xe2x80x9cHxe2x80x9d level second clock signal CLK1. That is, at the time t45, the voltage of the second clock signal CLK1 rises from a xe2x80x9cLxe2x80x9d level to a xe2x80x9cHxe2x80x9d level.
The transfer gate G11 is in an xe2x80x9cOFFxe2x80x9d state by the first clock signal {overscore (CLK1)} and the second clock signal CLK1 at the time t45. The operation of the master FF is stopped and the master FF holds the input signal data. At the same time, the transfer gate G13 is in an xe2x80x9cONxe2x80x9d state and starts the operation of the slave FF.
When the operation of the slave FF is started, a xe2x80x9cHxe2x80x9d level signal passes through a node N35 at the time t46. At the time t49, an inverted xe2x80x9cLxe2x80x9d level output signal {overscore (OUT)} is outputted.
In the above D-FF circuit 100, an internal set up time which is an effective accessible time for the input signal data is from the time t40 at which the data is inputted, to the time t45 at which the operation of the master FF is stopped. An effective internal tpd (Time for Propagation Delay) of the slave FF is the sum of the pass time of the slave FF and the pass time for generating the {overscore (CLK1)}, that is, from the time t45 to the time t49. Therefore, the operation speed (time) of the D-FF circuit 100 according to an earlier development is the sum of the set up time and the tpd, that is, from the time t40 to the time t49.
As described above, the D-FF circuit 100 according to an earlier development uses two signal having phases which are inverted each other. One signal stops the operation of the master FF to determine the set up time, and the other starts the operation of the slave FF to determine the tpd. Therefore, the set up time is almost restricted to the pass time of the master FF. The tpd is restricted to the pass time of the slave FF and the pass time for generating the CLK1. Because the operation speed of the D-FF circuit is determined by the sum of internal pass time, there is a problem that it is difficult to operate a D-FF circuit at high speed.
In order to solve the above-described problems, an object of the present invention is to operate a D-FF circuit at high speed in accordance with the clock signal generated by the clock signal generating circuit.
That is, in accordance with one aspect of the present invention, a D-FF circuit (for example, a D-FF circuit shown in FIG. 1A) for operating a master flip-flop and a slave flip-flop at each predetermined timing in accordance with a plurality of clock signals generated by a clock signal generating circuit (for example, a clock signal generating circuit 2 shown in FIG. 1B or a clock signal generating circuit 2xe2x80x2 shown in FIG. 3),
wherein the clock signal generating circuit generates the plurality of clock signals (for example, CLK, {overscore (CLK1)}, {overscore (CLK2)}, and CLK2 shown in FIG. 1B) at different timings,
the slave flip-flop starts operating (for example, a transfer gate G3 shown in FIG. 1A) in accordance with a clock signal (CLK and {overscore (CLK1)}) which is generated at an earlier timing than another clock signal generated by the clock signal generating circuit, and
the master flip-flop stops operating (for example, a transfer gate G1 shown in FIG. 1A) in accordance with a clock signal (CLK2 and {overscore (CLK2)}) which is generated at a later timing than another clock signal generated by the clock signal generating circuit.
According to the present invention, because the clock signal for stopping the operation of the master flip-flop is delayed and the clock signal for starting the operation of the slave flip-flop is advanced, it is possible to improve the set up time and the tpd. The operation speed of the D-FF circuit can be higher.
The clock signal generating circuit may comprise:
a first inverter (for example, an inverter 21 shown in FIG. 1B) for inverting an input clock signal (CLK) to output a first clock signal ({overscore (CLK1)}),
a buffer (for example, a buffer 22 shown in FIG. 1B) for delaying the first clock signal outputted from the first inverter for a predetermined time to output a second clock signal ({overscore (CLK2)}), and
a second inverter (for example, an inverter 23 shown in FIG. 1B) for inverting the second clock signal to output a third clock signal (CLK2);
wherein the slave flip-flop starts operating in accordance with the input clock signal (CLK) and the first clock signal ({overscore (CLK1)}) (for example, a transfer gate G3 shown in FIG. 1A), and the master flip-flop stops operating in accordance with the second clock signal ({overscore (CLK2)}) and the third clock signal (CLK2) (for example, a transfer gate G1 shown in FIG. 1A).
Because the clock signal for stopping the operation of the master flip-flop is delayed by the pass time of the buffer, it is possible to improve the set up time. Because the clock signal for starting the operation of the slave flip-flop is advanced by the pass time of the inverter, it is possible to improve the tpd. As a result, the operation speed (time) which is the sum of the set up time and the tpd, can be higher (shorten).
The clock signal generating circuit may comprise:
a first inverter (for example, an inverter 31 shown in FIG. 3) for inverting an input clock signal (CLK) to output a first clock signal ({overscore (CLK1)}),
a second inverter (for example, an inverter 32 shown in FIG. 3) for inverting the first clock signal outputted from the first inverter to output a second clock signal (CLK1),
a third inverter (for example, an inverter 33 shown in FIG. 3) for inverting the second clock signal outputted from the second inverter to output a third clock signal ({overscore (CLK2)}), and
a fourth inverter (for example, an inverter 34 shown in FIG. 3) for inverting the third clock signal outputted from the third inverter to output a fourth clock signal (CLK2),
wherein the slave flip-flop starts operating in accordance with the first clock signal ({overscore (CLK1)}) and the second clock signal (CLK1), and the master flip-flop stops operating in accordance with the third clock signal ({overscore (CLK2)}) and the fourth clock signal (CLK2).
The clock signal generating circuit comprises four inverters. The third clock signal and the fourth clock signal are used as clock signals for stopping the operation of the master flip-flop. The first clock signal and the second clock signal are used as clock signals for starting the operation of the slave flip-flop. Therefore, the timing at which the clock signals for stopping the operation of the master flip-flop are generated is delayed later than the timing at which the clock signals for starting the operation of the slave flip-flop are generated. The set up time can be improved. The operation speed of the D-FF circuit can be higher.
The clock signal generating circuit may comprise at least two inverters; a first inverter (for example, an inverter 31 shown in FIG. 3) inverting an input clock signal (CLK) to output a first clock signal ({overscore (CLK1)}) and a second inverter (for example, an inverter 32 shown in FIG. 3) inverting the first clock signal outputted from the first inverter to output a second clock signal ({overscore (CLK1)});
wherein the slave flip-flop starts operating in accordance with the input clock signal (CLK) and the first clock signal ({overscore (CLK1)}), and the master flip-flop stops operating in accordance with the first clock signal ({overscore (CLK1)}) and the second clock signal (CLK1).
The clock signal generating circuit comprises at least two inverters. The input clock signal and the first clock signal are used as clock signals for starting the operation of the slave flip-flop. The first clock signal and the second clock signal are used as clock signals for starting the operation of the master flip-flop. Therefore, the timing at which the clock signals for starting the operation of the slave flip-flop are generated is advanced earlier than the timing at which the clock signals for stopping the operation of the master flip-flop are generated. The tpd can be improved. The operation speed of the D-FF circuit can be higher.
The master flip-flop and the slave flip-flop may be made from CMOS.
Because the D-FF circuit is made from CMOS, the operation speed thereof can be higher.
In accordance with another aspect of the present invention, a D-FF circuit comprises:
a master flip-flop,
a slave flip-flop, and
a clock signal generating circuit for generating at least two clock signals at different timings respectively;
wherein the slave flip-flop starts operating in accordance with one clock signal which is generated by the clock signal generating circuit earlier than another clock signal, and
the master flip-flop stops operating in accordance with the another clock signal.